In order to protect the integrated circuit from damages possibly caused by electrostatic discharge (ESD) event, different efforts have been made by the industries. Transistors, such as grounded-gate NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), field-oxide MOSFET, output buffer transistors, or bipolar transistors, have been commonly used as primary ESD protection elements for integrated circuits. A diode also can be used as an ESD protection device by avalanche breakdown during the ESD event.
For ESD protection of an IC pin or a power bus, GGNMOS (grounded-gate NMOS) or GCNMOS (gate-coupled NMOS) can be used as the primary ESD protection. The drain of the NMOS transistor is connected to VDD or the IC pin, while the source of the NMOS transistor is connected to VSS. The gate is either grounded (GGNMOS), or coupled to VDD by a capacitor and to VSS by a resistor (GCNMOS). A bipolar transistor or other ESD protection circuit can also be used for ESD protection. The VDD to VSS voltage difference may increase rapidly to higher than 10 volts during an ESD event such as the following situations: (i) positive voltage stress of VDD pin to VSS pin, (ii) negative voltage stress of VSS pin to VDD pin, (iii) positive voltage stress on an input or I/O pin while the pin is connected to a pull-up (p+/nwell) diode or a pull-up PMOS, (iv) negative voltage stress on an input or I/O pin while the pin is connected a pull-down (n+/pwell) diode or a pull-down NMOS, or (v) positive voltage stress on one IC pin to another IC pin.
The ESD protection of a MOSFET (bipolar transistor as well) heavily depends on the triggering of a snap-back mechanism for conducting large amount of ESD current between the drain and source of MOSFET. To start, the high electric field at the drain-substrate junction causes impact ionization with generation of both minority and majority carriers. The minority carriers is collected at the drain (anode), while the majority carriers flow toward the substrate or pwell contact (cathode) causing a local potential build up in the pwell. When the local substrate potential is 0.8V higher than the adjacent n+ source potential, the source-substrate junction becomes forward biased. The forward-biased source-substrate junction injects minority carriers into the pwell. Some of those injected minority carriers are recombined in the substrate while the rest of them reached the drain-substrate junction to further enhance the impact ionization. And due to a continuous loop (positive feedback), the MOSFET gets into a low impedance (snapback) state to conduct large amount of ESD current.
In an ESD event, the triggering of an NMOSFET or bipolar ESD protection device is typically initiated by the avalanche breakdown of the reverse-biased diffusion-substrate junction (drain-substrate or collector-substrate junction). The trigger voltage is typically around 12 or 13 volt. It is of great advantage to lower the trigger voltage of a MOSFET (or bipolar transistor) during an ESD event. As the ESD protection occurs sooner, the transient voltage imposed on the I/O and internal circuit is lower which offers better overall ESD protection. When minority carriers (electrons) are present in the reverse-biased diffusion-substrate junction, due to carrier multiplication from impact ionization, the trigger voltage is reduced and the integrated circuit can be better protected in an ESD event.
The prior art, "ESD in Silicon Integrated Circuits" by A. Amerasekera and C. Duvvury, Chap. 3 and Chap. 4, John Wiley & Sons, 1995, hereinafter Ref. 1, describes in details the mechanism of ESD protection circuit. Among prior arts approaches, U.S. Pat. No. 5,366,908 discloses a process for fabricating a MOS device with protection against ESD. The Ref. 1 and U.S. Pat. No. 5,272,371 use a trigger device with a lower trigger voltage than that of the ESD protection device. Once the trigger device reaches avalanche break-down, lots of carriers are generated and some of them flow in the substrate to induce the trigger of the ESD protection device. Usually, additional implant or a special process recipe is needed, as disclosed in the U.S. Pat. No. 5,272,371, to adjust the trigger voltage of the trigger device, such that it is lower than the trigger voltage of the ESD protection device. The U.S. Pat. No. 5,218,222 discloses another ESD protection circuit which applicable for output and input pads. The U.S. Pat. No. 5,290,724 discloses another process for forming ESD protection circuit. The U.S. Pat. No. 5,508,224 discloses another process for forming ESD protection circuit. The U.S. Pat. No. 5,545,910 discloses another ESD protection circuit. Another prior art "Substrate Triggering and Salicide Effects on ESD Performance and protection Circuit Design in Deep Submicron CMOS Processes" presented by Amerasekera et al. in 1995 IEDM conference paper, lowers the trigger voltage of an ESD protection device by forward biasing a pull-up diode (p+/n-well diode) connected between the input pad and VDD bus. Through the reverse-biased nwell-to-pwell junction, some carriers are collected into the pwell to help triggering the ESD protection device in the pwell. Usually, a method of this nature creates a parasitic SCR (pnpn) path with a reverse-biased nwell/pwell junction, and the latch-up immunity issue therewith needs special design considerations.
U.S. Pat. No. 5,399,928 describes a method of generating negative voltage from a positive voltage source. The negative voltages are typically generated during IC operation and is used for back-bias generator or for the erase operation of Flash memory cells. U.S. Pat. No. 5,625,544 describes a voltage pump which generates a train of high voltage pulse with voltage values higher than Vdd during circuit operation. The pumped high voltage is used for EPROM erasing. U.S. Pat. No. 5,352,936 discloses technique by which high voltage charge pump is constructed by low voltage CMOS devices.